1. Field of the Invention
The present invention relates to a timer apparatus for detecting a pulse having an effective pulse width.
2. Description of the Prior Art
FIG. 17 is a block diagram showing the structure of a conventional timer apparatus. This timer apparatus is built in an apparatus such as a microcomputer. In the figure, reference numeral 1 denotes a counter counting the number of pulses of a clock signal C. Reference numeral 2 denotes a clock controlling circuit outputting a clock signal shown in FIG. 18(C) while an input signal A is at a low logic level shown in FIG. 18(A). The counter 1 is a down-counter that decreases the value of the count thereof by one by every input pulse.
The operation of the conventional timer apparatus is described below. The clock signal B is always supplied to the clock controlling circuit 2. As shown in FIGS. 18(A), 18(C), 18(Q), and 18(D), while the input signal A is at a low logic level, the clock signal passes through the clock controlling circuit 2 to the counter 1 as the clock signal C. The counter 1 counts the pulses in the clock signal C and when the value of count underflows, the counter 1 generates a count-up signal D of FIG. 18(D). Consequently, when a pulse having a pulse width corresponding to a value n set in the counter 1 as an initial value appears in the input signal A as shown in FIG. 18(A), the count-up signal D is generated. FIG. 18(Q) shows the value of the count of the counter 1, and the reference characters of the other diagrams correspond to the characters of respective signals in the block diagram.
Such a timer apparatus is used for the detection of an effective pulse width. The effective pulse width is defined as a pulse width used as a reference for dealing with an input pulse having a pulse width equal to the effective pulse width or more as an effective signal. Such a timer apparatus is used, for example, the detection of an input by a switch. In that case, the state of on or off of a contact of the switch is input as the input signal A. Consequently, when an on-state continues for a prescribed time or more, the count-up signal D is generated. The prescribed time is defined as a time necessary for the counter 1 to count the value n previously set as an initial value in the counter 1. The count-up signal D is used as, for example, an interrupt signal or a flag setting signal of a central processing unit (CPU). The CPU recognizes a depression of the switch by the occurrence of the interrupt signal or the turn on of a flag. If the on-state of the switch does not continue for a time necessary for the counter 1 to count the value n or more, the CPU regards the state as the occurrence of an on-state for a short time owing to a noise or the like, and concludes that the switch was not depressed.
If a simple counter is employed as the counter 1, a certain problem occurs. As shown in FIGS. 19(A), 19(C), 19(Q), and 19(D), if a pulse having a short pulse width F occurred before the occurrence of a pulse having a prescribed pulse width E, namely the effective pulse width, the value of count of the counter 1 advances during the period of the pulse width F. And then, when the pulse having the pulse width E is input into the counter 1, the counter 1 resumes counting from the value of count thereof at that point of time. As a result, the counter 1 underflows before the end of the period of the pulse width E. That is to say, the count-up signal D is output before the end of the period of the pulse width E. In FIGS. 18(A) and 19(A), a pulse width corresponding to three clocks of the clock signal C is shown as the prescribed pulse width.
Since the conventional timer apparatus is constructed as above, there is a problem that the count-up signal D is output though there is no input of a pulse having the effective pulse width.